FIG. 1 is a schematic circuit view of a conventional memory cell. As shown, the conventional memory cell 10 includes two P-type transistors P1, P2, four N-type transistors N1, N2, N3 and N4, a write word line WWL, a first write bit line WBL and a second write bit line WBLB. In the circuit structure of the memory cell 10 shown in FIG. 1, the N-type transistors N3, N4 both are controlled by the write word line WWL; specifically, both of the N-type transistors N3, N4 are controlled to be turned on by the write word line WWL when the memory cell 10 needs to perform data access. However, turning on the two N-type transistors N3, N4 at a same time may lead the memory cell 10 having a relatively poor anti-noise ability; wherein the anti-noise ability is usually measured/illustrated by the static noise margin (SNM).
FIG. 2 is a schematic plot illustrating the static noise margin of the memory cell 10 shown in FIG. 1; wherein the static noise margin is defined by the squares enclosed by two characteristic curves, and the area size of the static noise margin is proportional to the anti-noise ability of the memory cell 10. As shown, the area size of the static noise margin is relatively small due to the conventional circuit structure of the memory cell 10; thus, the conventional memory cell 10 has a relatively poor anti-noise ability and consequently the memory cell may result in errors while performing data access.